1. Field of the Invention
The present invention relates to a stacked semiconductor device, and more particularly relates to a stacked semiconductor device including a plurality of semiconductor chips electrically connected by through silicon vias.
2. Description of Related Art
A memory capacity required in semiconductor memory devices such as DRAM (Dynamic Random Access Memory) is increasing every year. In recent years, there has been proposed a method to meet this requirement. In this method, a plurality of memory chips are stacked and electrically connected via through silicon vias arranged on a silicon substrate (see Japanese Patent Application Laid-open No. 2007-158237).
Specifically, in a semiconductor memory device in which an interface chip having front end units such as interface circuits incorporated thereon and a core chip having back end units such as memory cores incorporated thereon are stacked, because read data that is read in parallel from the memory cores is supplied as it is to the interface chip without performing serial conversion, a large number of through silicon vias (approximately 4000 units in some cases) are required. However, the entire chip becomes defective when even one of the through silicon vias becomes defective, and if a plurality of the chips are stacked, all the chips become defective. Thus, to prevent the entire chip from becoming defective due to a defective through silicon via, auxiliary through silicon vias are sometimes provided in such semiconductor memory devices.
In the semiconductor device disclosed in Japanese Patent Application Laid-open No. 2007-158237, one auxiliary through silicon via is allocated to a group of through silicon vias constituted by a plurality of through silicon vias (for example, eight through silicon vias).
Further, because the through silicon vias are a type of wiring connecting a plurality of semiconductor chips, when there is a defective through silicon via, none of the semiconductor chips are allowed to use it, and this situation makes the use of an auxiliary through silicon via in place of the defective through silicon via essential. Therefore, it is essential to provide all the semiconductor chips with through silicon via switching information required for switching to the auxiliary through silicon via.
It is essential that the through silicon via switching information is nonvolatile information. However, when a circuit is provided in each of the semiconductor chips for storing the through silicon via switching information in a nonvolatile manner, it can lead to an increase in the chip area. This problem is not limited to semiconductor memory devices such as stacked DRAMs, but can occur to all stacked semiconductor devices in which a plurality of semiconductor chips are stacked and electrically connected to each other via through silicon vias.